International Conference on VLSI Design , January 1997 Overcoming the Serial Logic Simulation

We propose a new approach to parallelizing fault simulation in which the test set is partitioned among the available processors. The approach can be used for any of the sequential circuit fault simulation algorithms commonly used, and it can be implemented on various diierent parallel architectures. This approach for the rst time overcomes the limitations of serial logic simulation. In addition, the excessive redundant computations required in the traditional fault-partitioning approach are also considerably reduced. Signiicant improvements in speedup were observed as compared to previous approaches. An average speedup of 5.7 was obtained for test set partitioning over 10 processors for the benchmark circuits studied. Although pessimistic fault coverage may be reported in some cases, the proposed approach was found to be very accurate for the circuits studied. Fault simulation is an important step in the electronic design process and is used to identify faults that cause erroneous responses at the outputs of a circuit for a given test set. For each test vector, the good circuit (fault-free circuit) and the faulty circuits are simulated. If the output responses of a faulty circuit diier from those of the good circuit, then the corresponding fault is detected, and the fault can be dropped from the fault list, speeding up simulation of subsequent test vectors. A fault simulator can be run in stand-alone mode to grade an existing test set, or it can be interfaced with a test generator to reduce the number of faults that must be explicitly targeted by the test generator. Due to the long execution times for large circuits, several algorithms have been proposed for parallelizing sequential circuit fault simulation 1]. A circuit partitioning approach to parallel sequential circuit fault simulation is described in 2]. The algorithm was implemented on a shared-memory mul-tiprocessor. The circuit is partitioned among the processors , and since the circuit is evaluated level-by-level with barrier synchronization at each level, the gates at each level should be evenly distributed among the processors to balance the workloads. An average speedup of 2.16 was obtained for 8 processors, and speedups for ISCAS89 circuits s5378 and s35932 were 3.29 and 4.86, respectively. This approach is most suitable for a shared-memory architecture for circuits with many levels of logic. Algorithmic partitioning was proposed for concurrent fault simulation in 3]]4]. A pipelined algorithm was developed, and speciic functions were assigned to each processor. An estimated speedup of 4 to …